1. Field of the Invention
The present invention relates to a phase detector, and more particularly, to a phase detector applied in a Clock and Data Recovery Circuit (CDR).
2. Description of the Prior Art
In the test of CDR, normally the Jitter Tolerance (JTOL) is tested to decide the ability of CDR. However, the JTOL of CDR is generally affected by some factors such like the type of data, the response time of circuit, the bandwidth of the CDR. For the type of data, the phase detector of traditional CDR can't immediately generate the corresponding phase-leading (early) signal or phase-lagging (late) signal for some specific types of the input data signal such like a plurality of consecutive “0”s or “1”s, so the speed of phase calibration of clock signal is thus delayed. In addition, for the response time of circuit, because a delay phenomenon may exist between circuits, the current direction of phase adjustment of the clock signal might be opposite to the true direction of phase adjustment, so the error of phase calibration might be caused by the phase adjustment.